Design for Test Engineer

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Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Design and develop DFT (Design-for-Test) architecture. Verify ATPG (Automatic Test Pattern Generation) design rules. Perform ATPG QoR (Quality of Results) for TTR (Test time reduction) and silicon diagnosis. Perform ATPG pattern generation and ATE (Automatic Test Equipment) bring-up and debug. Code Verilog RTL for DFT. Work with designers on STA (Static Timing Analysis), physical, power, and logical issues. Work with Test Engineering for ATE bring-up. Work with DV (Design Verification) team to verify DFT implementations in RTL and Gate level and implement ECO’s. International travel required 6%. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $163,872 - $205,500/yr and your base pay will depend on your skills, qualifications, experience, and location. PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Minimum Qualifications

Master’s degree or foreign equivalent in Electrical Engineering, Computer Engineering, or related field and 2 years of experience in the job offered or related occupation. Experience and/or education with the following skills: Perl to automate and execute design flows ATPG, Test compression, Tessent to perform Scan pattern generation and fault coverage Scan diagnosis to analyze silicon failures from ATE and improve yield and manufacturing process Verilog, System Verilog for design and verification STA for Timing Analysis

Preferred Qualifications

N/A