Senior RTL Design Engineer, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
• 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
• Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques.
• Experience with a scripting language like Perl or Python.

Preferred qualifications:

• Master's or PhD degree in Electrical Engineering, Computer Engineering or Computer Science.
• Experience with ASIC design methodologies for clock domain checks, reset checks and low power design.
• Knowledge in one of these areas: Processor Cores, Buses/Fabric/NoC, Debug/Trace, Interrupts, Clocks/Reset.
• Knowledge of FPGA and emulation platforms.
• Knowledge of ASIC Verification or DFT.

About the job:

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities:

• Manage microarchitecture definition for a subsystem.
• Lead integration of internal or external IP.
• Manage microarchitecture definition of a small to medium size IP.
• Perform RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks.
• Participate in test plan and coverage analysis of the sub-system and chip-level verification.