Physical Design Engineer, Static Timing Analysis

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.
  
• 7 years of experience in static timing (i.e., full chip timing signoff ownership, constraint authoring and verification, full chip static timing analysis and timing ECO creation, timing margins).
• Experience with Electronic Design Automation (EDA) tools (i.e., Primetime, Tempus, Timevision, STAR-RC) and EDA Tcl commands for timing analysis, timing closure, parasitic extraction, noise glitch, crosstalk.

Preferred qualifications:

• 10 years of experience in the domain of static timing analysis.
• Experience leading one or more aspects of physical design or physical design flow/methodology, to successful tape-outs and shipping silicon.
  
• Experience in extraction of design parameters, QoR metrics, and analyzing data trends.
  
• Knowledge of semiconductor device physics and Simulation Program with Integrated Circuit Emphasis (SPICE) simulation and full-chip static timing topics, including clocking, timing exceptions, time budgeting, IO interface timing, ECOs, and constraint verification.
  

About the job:

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will work on the physical implementation of Application-specific integrated circuits (ASIC) using advanced technology nodes. You will work on timing margin derivation, constraint development and validation, and timing closure of large, complex high performance compute ASICs. You will develop static timing methodologies, margins, automation scripts, and write documentation. You will perform technical evaluations of vendors, tools, methodologies, and will provide recommendations. Additionally, you will work with architecture, logic design, and Design for testing (DFT) teams to understand and implement their requirements.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities:

• Own timing constraint creation and validation, perform timing analysis and timing Engineering Change Order (ECO) creation, and oversee final timing sign-off for complex ASICs.
• Participate in both static timing analysis methodology development and support, as well as chip implementation and timing signoff execution.
• Develop, support and execute implementation flows around industry-standard static timing and parasitic extraction tools.
  
• Develop, support and execute implementation flows around industry-standard static timing and parasitic extraction tools.
• Debug flow issues reported by your wider team and work with EDA vendors to resolve them where necessary.