SOC/ASIC Physical Design Engineer (Silicon Engineering) - job 1 of 2
Skills
- Proficiency in ASIC/SOC physical design and signoff flows.
- Experience with industry-standard EDA tools and understanding their algorithms.
- Knowledge of FinFET/CMOS solid state physics and digital design principles.
- Familiarity with CMOS power dissipation, analog circuit design, and physical design.
- Scripting skills including csh/bash, Perl, Python, TCL, and Makefile.
Responsibilities
- Perform partition synthesis and physical implementation steps including synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, and physical verification checks.
- Develop and improve physical design methodologies and automation scripts for implementation.
- Collaborate cross-functionally with ASIC design teams on architectural feasibility, timing, power, and area design targets.
- Identify and resolve design, timing, congestion, and flow issues and drive execution.
- Run, debug, and resolve signoff closure issues in static timing analysis (STA), noise, logic equivalency, electromigration, and voltage drop.
Education
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science.
Benefits
- Comprehensive medical, vision, and dental coverage.
- 401(k) retirement plan with company contributions.
- Short and long-term disability, life insurance.
- Paid parental leave and 3 weeks paid vacation plus 10+ paid holidays.
- Employee Stock Purchase Plan with discounted stock options.
- Potential discretionary bonuses and long-term incentives.
Average salary estimate
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