Digital Design Engineer
We are hiring a Digital Design Engineer to contribute to our edge and FPGA development product line. This role focuses on RTL development and simulation using industry-standard tools. You will be joining a team that values technical rigor, ownership, and collaboration across disciplines.
Responsibilities
- Design and implement digital logic using VHDL and Verilog
- Perform RTL simulation and debugging using tools such as: Cadence Xcelium, Synopsys VCS, Xilinx xsim
- Write Python scripts for test automation, simulation workflows, or tooling
- Work within a Linux command-line development environment
- 3+ years of experience with both VHDL and Verilog
- 3+ years of experience with Python
- 5+ years of experience with RTL simulation and debugging using any of the following: Cadence Xcelium, Synopsys VCS, Xilinx xsim
- Comfortable working in Linux and command-line environments
- Experience with Xilinx Vivado or similar FPGA toolsets
- Familiarity with signal processing building blocks (e.g., FIR/IIR filters)
- Bonus: Interest in or familiarity with LLM models and their limitations
- Health Care Plan (Medical, Dental & Vision).
- 401k with 5% matching.
- Paid Time Off (Uncapped Vacation, plus Sick & Public Holidays).
- Flexible hybrid work arrangement.
- Relocation assistance for qualifying employees.
Average salary estimate
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